›› 2011, Vol. 31 ›› Issue (3): 56-61.doi: 10.3780/j.issn.1000-758X.2011.03.009

• 技术交流 • 上一篇    下一篇

多码率串并Viterbi译码器优化设计

王闰昕, 刘荣科, 赵岭   

  1. (北京航空航天大学电子信息工程学院, 北京 100191)
  • 收稿日期:2010-08-31 修回日期:2010-11-19 出版日期:2011-06-25 发布日期:2011-06-25
  • 作者简介:王闰昕 1987年生,2009年毕业于北京航空航天大学电子信息工程专业,现为北京航空航天大学通信与信息系统专业硕士研究生。研究方向为信道编解码。

Optimal Design of Serial-parallel Viterbi Decoder with Multi-rate Convolutional Codes

WANG  Run-Xin, LIU  Rong-Ke, ZHAO  Ling   

  1. (School of Electronics and Information Engineering,Beihang University,Beijing 100191)
  • Received:2010-08-31 Revised:2010-11-19 Online:2011-06-25 Published:2011-06-25

摘要: 为了降低Viterbi译码器的硬件复杂度,对其结构特点进行了研究。通过分析卷积码的特点,对支路度量单元进行了优化,使每次所计算的支路度量值从16个减少到4个。使用灵活快速的回溯算法实现了回溯参数可配置;用同一个硬件结构实现了对CCSDS标准中的多码率删余卷积码的译码。优化结构与传统串并结构相比,译码速度相同,硬件资源可节省60%;与传统串行结构相比,硬件资源基本相同,译码速度达到了串行结构的8倍。

关键词: 卷积码, 串并结构, 多码率, 维特比译码器, 优化设计

Abstract: In order to reduce the hardware complexity, the structural characteristics of the Viterbi decoder were studied. The branch measure unit was optimized by analyzing the characteristics of convolutional codes. Result show that the calculated branch metric value reduces from 16 to 4. The parameters of trace back unit can be configured by the backtracking algorithm with high flexibility and speed. Besides, the multirate punctured convolutional codes of  CCSDS are acomplished by the same hardware architecture. 60% of the resources are saved compared with the normal serial-parallel structure with the same decoding speed. The throughput is as 8 times as the normal serial-parallel structure with the same hardware resources.

Key words: Convolutional code, Serial-parallel structure, Multi-rate〓Viterbi decoder, Optimal design